During conventional semiconductor manufacturing processes, numerous coatings are applied to and removed from semiconductor wafers. One of the processes used is lithography, which defines photographically the surface geometry of the various integrated-circuit (IC) components on the wafer. Lithography starts with applying a layer of photoresist over the semiconductor wafer, followed by stepping. During stepping, the deposited photoresist is selectively exposed to light according to a predetermined layout disposed on a mask. The exposed photoresist is rendered soluble (in the case of positive photoresist) and is subsequently removed using a chemical developer, leaving the mask pattern on the wafer. The semiconductor wafer then undergoes etching with the remaining photoresist protecting the unexposed areas of the wafer from the etchant. Thus, the substrate layer of the wafer directly underneath the photoresist layer is etched in accordance with the mask pattern. The semiconductor wafer is generally subjected to multiple iterations of these and other processes before all IC components are fully fabricated on the wafer.
With reference to Prior Art FIG. 1, a top view of semiconductor wafer 5 is shown. A semiconductor wafer 5 is generally divided into numerous identical regions 12 called dies or exposure shots. Each die 12 will be photographically exposed according to a mask pattern after photoresist has been applied to the wafer 5 as described above. Thus, when the fabrication process is completed, each die 12 will contain the complete circuitry of an IC chip. These dies 12 are delineated on the semiconductor wafer 5 by scribe lines or scribe alleys 15. Generally, scribe alleys 15 are disposed on the upwardly-facing surface of the semiconductor wafer 5 in two mutually perpendicular directions, namely, the x-direction and the y-direction, thus dividing the wafer 5 into multiple square or rectangular dies 12. It is crucial that the array of dies 12 on the semiconductor wafer 5 in Prior Art FIG. 1 and the corresponding masks line up exactly during every lithography step so that the different mask patterns can be accurately superimposed on the wafer 5. To enable accurate positioning of the wafer 5 relative to a mask within a wafer stepper, alignment features, not shown in Prior Art FIG. 1, are disposed along the scribe alleys 15 of the wafer 5.
Prior Art FIG. 2 is a top view of an intersection of two scribe alleys 15 disposed perpendicular to each other with an alignment feature 10 disposed on the bottom surface of one of the two scribe alleys 15. Four neighboring dies 12 are also partially shown. An alignment feature 10 is a small trench created by performing an etch into the bottom surface of the scribe alley 15. Using several alignment features 10 on the semiconductor wafer as position markers, a wafer stepper can accurately position the wafer during various fabrication steps.
Once the alignment features 10 have been created in the scribe alleys 15 of a wafer 5, the wafer 5 is subjected to additional processing steps. In particular, to perform a lithography step, photoresist has to be first applied over the upwardly-facing surface of the wafer 5 before photographic exposure, as described above. Commonly, a desired amount of photoresist is centrally dispensed onto the upwardly-facing surface of the semiconductor wafer 5. Rotational motion of the wafer 5 causes the photoresist to spread radially outward from the center portion of the semiconductor wafer 5 towards the edge of the semiconductor wafer 5 such that the entire upwardly-facing surface of the wafer 5 is coated with a layer of photoresist.
However, it has long been recognized in the semiconductor processing art that the presence of alignment features result in the formation of comet tails during subsequent spin-on deposition of photoresist on the surface of a wafer. Referring now to Prior Art FIG. 3, a top view of a prior art alignment feature 10 disposed on the bottom surface of a scribe alley 15 is shown. In Prior Art FIG. 3, photoresist has been applied to the upwardly-facing surface of the wafer by a spin-on process as described above, and a comet tail 35 originating from the alignment feature 10 and parts of four neighboring dies 12 are also shown. A comet tail 35 is an area of the upwardly-facing surface of the wafer which is not covered or which is not as thickly covered by photoresist after the spin-on process. In other words, the spin-on process does not adequately coat the complete surface of the wafer with photoresist. Instead, the spin-on process leaves various "bald" areas with little or no photoresist. These bald areas originate from various prior art alignment features 10 and are shaped like the tail of a comet on the wafer surface. Although the above description specifically recites problems associated with comet tail formation in photoresist spin-on processes, it will be understood that comet tail formation is a problem associated with numerous other spin-on processes. That is, the problem of comet tail formation is not limited solely to photoresist spin-on processes.
Referring next to Prior Art FIG. 4, a top view of a wafer with multiple comet tails 35 originating from several prior art alignment features 10 disposed along scribe alleys 15 is shown. Since the areas on the wafer affected by the comet tails 35 are not coated by photoresist, these areas will not be able to capture proper photographic exposure during stepping. Hence, the desired mask pattern cannot be developed in the affected areas. Any die 12 that is affected by a comet tail 35 will consequently yield a defective die. As is illustrated in Prior Art FIG. 4, a total of 15 dies are affected by the three comet tails 35 shown. Even though it has long been perceived by persons skilled in the semiconductor processing art that the formation of comet tails 35 is induced by prior art alignment features 10, no satisfactory solution has been developed to avoid the formation of comet tails 35 caused by prior art alignment features 10. As such, prior art alignment features 10 adversely affect the yield of semiconductor manufacturing processes by inducing comet tail formation in spin-on processes, thereby resulting in the production of defective dies.
Next, the formation of prior art alignment features and the physical characteristics of these alignment features are further described. As one of numerous steps in the semiconductor fabrication process, etching of alignment features is usually preceded by another processing step. Frequently, a separate etching step, such as one for the removal of an oxide layer, is performed prior to the etching of alignment features. More particularly, either of two common etching techniques, wet etching and dry etching, can be selected in the design of process flow within the fabrication process (process integration). Wet etching involves immersing a batch of lithographically treated wafers in a liquid chemical etchant, such as hydrochloric acid (HCl) or potassium hydroxide (KOH), so that the areas of the wafers not masked by photoresist are etched away by the etchant while the masked areas are shielded from the chemical reaction. In contrast, dry etching, also known as plasma etching, typically involves bombarding photoresist-covered wafers, one wafer at a time, with an accelerated beam of reactive ions so that the uncovered areas of the wafer is etched away, as is the case in reactive ion etching (RIE). Due to the batch processing of wafers in wet etching versus the sequential treatment of individual wafers in dry etching, wet etching is generally perceived to be more cost effective than dry etching and is thus commonly selected over dry etching in process integration.
Unfortunately, areas of a wafer that are formed by wet etching frequently exhibit a characteristic cross-sectional profile that is non-conducive to the deposition of photoresist over the wafer in subsequent processing steps. Prior Art FIG. 5 more particularly illustrates the characteristic cross-sectional profile of a prior art alignment feature 10 that is formed by wet etching. Prior Art FIG. 5 is a cross-sectional view of a scribe alley 15 on a wafer with an alignment feature 10 disposed on the bottom surface 16 of the scribe alley 15. Two neighboring dies 12 are also shown with scribe alley 15 separating the dies 12. In this instance, the prior art alignment feature 10 has been wet etched into the bottom surface 16 of the scribe alley 15. In particular, wet etching routinely results in the formation of protruding structures 53 and 54, which are disposed at or near the intersection of the alignment feature's sidewalls 51 and 52 and the bottom surface 16 of the scribe alley 15, and recessed or hollow areas 55 and 56 directly underneath protruding structures 53 and 54, as shown in Prior Art FIG. 5.
Alternatively, in the formation of an alignment feature, a wet etching step is followed by a dry etching step. Prior Art FIG. 6 shows a cross-sectional view of an alignment feature 10 etched into the bottom surface 16 of a scribe alley 15 by a combination of wet etching and dry etching, with two dies 12 on opposite sides of the scribe alley 15. In Prior Art FIG. 6, alignment feature 10 has sidewalls 61 and 62, each of which comprises two distinct and corresponding segments. Specifically, sidewall 61 exhibits an upper segment 61a formed by wet etching and a lower segment 61b formed by dry etching. As explained above with respect to Prior Art FIG. 5, the peculiar profile of upper portion 61a with protruding structure 63 and recessed area 65 is attributable to the characteristic etching action of wet etching. On the other hand, the relatively straight lower segment 61b is a typical result of dry etching action. Likewise, for the same reasons, sidewall 62 has an upper segment 62a and a lower segment 62b that correspond, respectively, to upper segment 61a and lower segment 61b of sidewall 61, with upper segment 62a further comprising protruding structure 64 and recessed area 66. Thus, the combination of a first wet etching step and a subsequent dry etching step leads to the formation of alignment feature 10 as depicted in Prior Art FIG. 6.
Prior art photoresist spin-on processes have attempted to alleviate the deleterious effects of comet tails by dispensing excessive amounts of photoresist on the semiconductor wafer during the spin-on application of photoresist. Simply stated, in these prior art spin-on processes, additional photoresist is dispensed until the comet tails that are initially formed by a first wave of outwardly-spreading photoresist are finally filled up by subsequent waves of outwardly-spreading photoresist. In other words, a huge excess of photoresist is dispensed to cover up the comet tails caused by prior art alignment features. As an example, in a typical prior art spin-on process, 5 or more milliliters (ml) of photoresist is dispensed for coating each wafer such that all comet tails are covered up. However, a large proportion (approximately 98%) of the dispensed photoresist is spun off rather than remaining on the wafer for photographic exposure. Thus, dispensing such a voluminous amount of expensive photoresist in these prior art spin-on processes inevitably results in a substantial waste of photoresist and higher manufacturing costs for the overall fabrication process.
Thus, a need exists for an alignment feature and a production method which do not result in the formation of deleterious comet tails during subsequent processing steps. A further need exists for an alignment feature and a production method which eliminate the necessity to waste expensive spin-on material. Still another need exists for an alignment feature and a production method which meet the above needs without incurring substantial capital expenditures for new processing equipment or extensive retrofitting of current processing equipment.